In an embodiment, the external electrodes are U-shaped. More specifically said, the first substrate further has a second main surface opposite to the first main surface, and a first side surface that extends from the first main surface to the second main surface, wherein the protective envelope extends along the second main surface and/or the first side surface, wherein the first external electrode covers a part of the protective envelope adjacent to at least one of the first main surface, the second main surface, and/or the first side surface. In this way, for example in case the first and second external electrode cover the part of the protective envelope adjacent to both the first main surface and the second main surface, the packaged semiconductor product can be mounted to a surface, for example a surface of a printed circuit board, irrespective whether the electronic structure faces towards or away from the surface of the printed circuit board. In addition, such a packaged semiconductor product can have a thickness, measured in a direction transverse to the first and second main surface, of at most 150 micrometer, or even of at most 100 micrometer. Such a small thickness of the packaged semiconductor product can advantageously reduce weight and size of an electric product that includes the packaged semiconductor product.
In an embodiment, a recess is present in the semiconductor substrate adjacent to an edge of the first side surface and the first main surface. Suitably, such recess is present at an edge with a further, second side surface, i.e. in a corner of the packaged device. However, it is not excluded that such recess extends over a larger portion, up to constituting a groove along the complete first side surface. In this embodiment, a probability of damage, such as delamination of the protective envelope from the first substrate, is reduced. By filling the recess, the protective envelope can engage on the recess. In practice, delamination might occur during a production process of the first semiconductor device, but might also occur during use of the first semiconductor device, in particular during use in harsh circumstances, for example with large temperature fluctuations leading to thermo-mechanical stress and/or with high mechanical loading such as mechanical shocks. Such delamination can lead to direct electrical contact between the first and/or second external electrode and the first substrate. By preventing delamination during manufacturing according to the invention, a yield of manufacturing can be improved.
More specifically, the recess is provided with a recess surface with encloses an angle with both the first side surface and the first main surface in a range between 45 and 135 degrees, more preferably between 60 and 120 degrees, and even more preferably between 75 and 105 degrees. In this manner, adequate engagement between the protective envelope and the first substrate is enabled. Preferably, the recess surface is rounded. Both the angles and the surface shape allow the recess to be generated by punching, lasering and/or etching.
The protective envelope extending along the passivation layer and/or engaging on the recess both offer the significant advantage of an increased robustness of the packaged semiconductor product against mechanical shocks, and against damage from thermomechanical stress as a result of, possibly repeated, variation in temperature of the packaged semiconductor product. This is achieved by the protective envelope engaging, for example gripping, on the recess and/or on the first main surface.
In an embodiment, a boundary of the first passivation layer substantially extends up to a boundary of the first main surface. This has the advantage that a lot of the first semiconductor devices, included by a semiconductor wafer, can be provided with the first passivation layer in one blanket deposition step. In an alternative embodiment, the boundary of the first passivation layer does not extend completely up to the boundary of the first main surface. In this case, a probability of developing cracks in the first passivation layer near the boundary of the first main surface, as a result of a separation process, such as sawing, of the first semiconductor devices from the semiconductor wafer, is reduced.
In an embodiment, the first substrate has first additional side surfaces that extend from the first main surface to the second main surface, and the protective envelope extends along the second main surface, the first side surface, and the first additional side surfaces, wherein the first external electrode covers the part of the protective envelope adjacent to the first main surface, the second main surface, and the first side surface. In particular, the second external electrode covers the part of the protective envelope adjacent to the first main surface, the second main surface, and at least one of the first additional side surfaces. This offers a practical version of the packaged semiconductor product according to the invention.
In an embodiment, the packaged semiconductor product includes a second semiconductor device having a second substrate and being provided with a second passivation layer and a second electronic structure, wherein the second substrate is embedded in the protective envelope and has a third main surface that faces a second opening of the protective envelope, the second electronic structure being integrated with the second substrate along the third main surface and having a third and a fourth contact region, wherein the second passivation layer substantially covers the third main surface and the second electronic structure and leaves free the third and fourth contact region, wherein the second external electrode is electrically coupled to the fourth contact region and is electrically connected to the second contact region via the fourth contact region, the second electronic structure, the third contact region, and a conducting structure from the third contact region to the second contact region, wherein the protective envelope forms an electrically isolating structure between the first substrate and the second substrate. In this way good electrical isolation between the first and second substrate can be achieved outside the conducting structure. This is important for example when the first and second semiconductor device form a cascade of electrically connected diode pairs and these diode pairs need to be electrically isolated from each other outside the conducting structure, as can for example be required in ESD protection with high voltage triggering.
In an embodiment, an electrically isolating layer portion extends between the conducting structure and the first and/or second passivation layer. In this way, a probability of electrical shorts from the conducting structure through respectively the first and/or second substrate is further reduced. The isolating layer portion can improve electrical isolation of the conducting structure.
In an embodiment, the isolating layer portion is arranged to extend between substantially all of the conducting structure and the first substrate and/or between substantially all of the conducting structure and the second substrate. In this way, direct contact between the conducting structure and the first and second passivation layer is substantially prevented. In particular, this offers a way of connecting the first and second semiconductor device. In a similar way, a third semiconductor device can be connected to the second semiconductor device, a fourth semiconductor device can be connected to the third semiconductor device, and so on. In case each semiconductor device includes a diode, such a cascade of semiconductor devices may for example increase a triggering voltage of a semiconductor device for ESD protection.
In an embodiment, at least part of the isolating layer portion is formed by an extension of the protective envelope that extends between the first passivation layer and the conducting structure towards the second contact region and that possibly extends between the second passivation layer and the conducting structure towards the third contact region. This increases the symmetry of the packaged semiconductor product and consequently facilitates a production process of the packaged semiconductor product.
In an embodiment, the packaged semiconductor product includes at least one of a passive component, a structure for combined passive functions, and an integrated circuit structure. In particular, the semiconductor product includes only one passive component, such as a resistor, an inductor, a capacitor or a diode.
In an embodiment, the packaged semiconductor product includes at least one of a back-to-back pair of Zener diodes and a back-to-back pair of Avalanche diodes.
In an embodiment, the packaged semiconductor product is manufactured in a first production environment, for example an integrated circuit foundry environment or wafer fab, and the protective envelope, the optional conducting structure and/or the isolating layer portion are applied in a second production environment that may be related to the first production environment, for example a post-processing zone in a wafer fab. This embodiment has the advantage that it combines well with emerging packaging techniques, such as redistributive chip packaging or embedded wafer level packaging. Such a process flow is different from a conventional process flow, wherein packaging is performed outside the first production environment, for example in a chip assembly environment where conditions are less clean compared to the first and second production environment.
The invention also provides an electric product including a packaged semiconductor product according to the invention. Such a product can for example be a mobile phone, a computer such as a lap top computer, an MP3-player, or a television or monitor, for example provided with a liquid crystal display or a cathode ray tube. In particular, the dimensions of the packaged semiconductor product are important for an electric product according to the invention, as is for example the case in an electric product for medical use, in a wireless electric product, and in a portable electric product.
It is another object of the invention to provide a method for manufacture of a packaged semiconductor product with improved protection against coating failure.
Accordingly, the invention provides a method that includes the steps of: d) moulding the protective envelope around the first semiconductor device, so that the first substrate is embedded in the protective envelope and the first main surface faces a first opening of the protective envelope, and further moulding the protective envelope along a part of the first passivation layer; and e) applying the first and second external electrode with the first external electrode coupled to, and preferably in direct electrical contact with the first contact region and the second external electrode electrically coupled to the second contact region.
In an embodiment, step d) includes curing the protective envelope. Curing may include heating the protective envelope.
In an embodiment, step c) includes placing the first semiconductor device on a carrier with the first passivation layer facing the carrier, and step d) includes moulding the protective envelope around the first semiconductor device along the part of the first passivation layer by partly filling a space between the first passivation layer and the carrier. This is an efficient and well-controlled way of obtaining an extension of the protective envelope that extends between the first passivation layer and first external electrode. Partly filling the space may be performed under compression and by using a flexible carrier, so that the space becomes filled by underfilling the first semiconductor device.
In an embodiment, the method includes carrying out the steps a)-e) for a plurality of first semiconductor devices, wherein the carrier is common for the plurality of first semiconductor devices and the protective envelopes of the plurality of first semiconductor devices are formed by a common moulded structure, wherein a moulded wafer is obtained after steps a)-d) and possibly after step e) that includes the plurality of first semiconductor devices and the common moulded structure, including the step of: f) dividing the moulded wafer into separate packaged semiconductor products, each packaged semiconductor product including one or more semiconductor devices of the plurality of first semiconductor devices. Such a method offers an efficient way of manufacturing the plurality of packaged semiconductor products, wherein process steps, which are for example related to handling, deposition, or patterning, can be carried out for the plurality of the semiconductor devices at the same time. The moulded wafer may be obtained after step e) for example in case the first and second external electrode are part of a redistribution layer, that is deposited before step f) is carried out. The moulded wafer may be obtained before step e) for example in case the first electrode is deposited on the protective envelope along the first side surface.
In an embodiment, the method includes separating the first semiconductor device from a semiconductor wafer by sawing using a saw with a first thickness creating a notch in the semiconductor wafer and sawing along the notch using a saw with a second thickness that is smaller than the first thickness, thus obtaining a second side surface of the first substrate that extends from the first main surface, which first side surface is provided with a recess adjacent to an edge of the second side surface and the first main surface. Preferable, the recess extends at the edge of the second side surface and the first main surface. This is an efficient way of obtaining the recess, as sawing equipment for sawing the wafer usually is readily available. By filling the recess, the protective envelope engages on the recess, hindering the occurrence of delamination between the protective envelope and the first substrate and reducing a probability of occurrence of shorts from the first external electrode to the first substrate or vice versa.